1. Field of the Invention
The invention pertains generally to computers. In particular, the invention pertains to testing computers that have multi-core architecture.
2. Description of the Related Art
Multi-core computers include at least two cores connected to other parts of the system through a common interface. A ‘core’ in this context includes a processor and typically also includes one or more levels of cache memory dedicated to the processor, while additional levels of cache memory may be shared by the processors of multiple cores over a common bus. Each core can execute instructions and send data requests over the common bus independently of the other cores, with arbitration logic to determine which core obtains access to the common bus. However, each core is indirectly affected by the transactions of the other cores because of congestion that results when heavy data traffic from the multiple cores exceeds the bandwidth of the common bus. The hierarchy of shared and non-shared cache memories can also cause congestion. For each transaction issued from one of the cores to its dedicated cache, snoop logic may send a query request to the other cores to check their dedicated caches for data coherency. In addition to causing congestion on the common bus, such requests, referred to as self-snoop, are an overhead burden for the cores since self-snoop adds to the requests that the cores need to process. If a query request hits a modified cache line in a core, the core must write-back the line to update other caches, adding to the overhead burden of the cores. With multiple cores each generating requests and triggering self-snoop operations, the cache memories and bus logic can be overwhelmed by too much data traffic, creating bottlenecks in the processing operations of the system.
In addition to data bandwidth considerations, the order in which transactions are placed on the bus may also affect performance. This order may be affected by the interaction of various parts of the system during periods of heavy data traffic.
Post-silicon data-flow stress testing is used to determine the effects of such heavy data traffic in a multi-core computer system by generating high levels of activity in the cache memories and over the common bus. Conventional testing relies on instruction-level tests running in each core, hoping to get the desired interaction between the cores. Unfortunately, since each core operates relatively independently of the other cores, achieving the desired level of interaction is both difficult and hard to measure with instruction-level tests executed from the cores.